Update archspec to v0.2.5-dev (7e6740012b897ae4a950f0bba7e9726b767e921f) (#45721)
This commit is contained in:
Massimiliano Culpo
Harmen Stoppels
parent
4da21d8f60
commit
bd9186038a
5 changed files with 168 additions and 37 deletions
2
lib/spack/external/__init__.py
vendored
2
lib/spack/external/__init__.py
vendored
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@ -18,7 +18,7 @@
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* Homepage: https://pypi.python.org/pypi/archspec
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* Usage: Labeling, comparison and detection of microarchitectures
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* Version: 0.2.4 (commit 48b92512b9ce203ded0ebd1ac41b42593e931f7c)
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* Version: 0.2.5-dev (commit 7e6740012b897ae4a950f0bba7e9726b767e921f)
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astunparse
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----------------
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12
lib/spack/external/archspec/cpu/detect.py
vendored
12
lib/spack/external/archspec/cpu/detect.py
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@ -47,7 +47,11 @@ def decorator(factory):
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def partial_uarch(
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name: str = "", vendor: str = "", features: Optional[Set[str]] = None, generation: int = 0
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name: str = "",
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vendor: str = "",
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features: Optional[Set[str]] = None,
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generation: int = 0,
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cpu_part: str = "",
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) -> Microarchitecture:
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"""Construct a partial microarchitecture, from information gathered during system scan."""
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return Microarchitecture(
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@ -57,6 +61,7 @@ def partial_uarch(
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features=features or set(),
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compilers={},
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generation=generation,
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cpu_part=cpu_part,
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)
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@ -90,6 +95,7 @@ def proc_cpuinfo() -> Microarchitecture:
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return partial_uarch(
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vendor=_canonicalize_aarch64_vendor(data),
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features=_feature_set(data, key="Features"),
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cpu_part=data.get("CPU part", ""),
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)
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if architecture in (PPC64LE, PPC64):
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@ -345,6 +351,10 @@ def sorting_fn(item):
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generic_candidates = [c for c in candidates if c.vendor == "generic"]
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best_generic = max(generic_candidates, key=sorting_fn)
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# Relevant for AArch64. Filter on "cpu_part" if we have any match
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if info.cpu_part != "" and any(c for c in candidates if info.cpu_part == c.cpu_part):
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candidates = [c for c in candidates if info.cpu_part == c.cpu_part]
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# Filter the candidates to be descendant of the best generic candidate.
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# This is to avoid that the lack of a niche feature that can be disabled
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# from e.g. BIOS prevents detection of a reasonably performant architecture
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@ -2,9 +2,7 @@
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# Archspec Project Developers. See the top-level COPYRIGHT file for details.
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#
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# SPDX-License-Identifier: (Apache-2.0 OR MIT)
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"""Types and functions to manage information
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on CPU microarchitectures.
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"""
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"""Types and functions to manage information on CPU microarchitectures."""
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import functools
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import platform
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import re
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@ -65,21 +63,24 @@ class Microarchitecture:
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passed in as argument above.
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* versions: versions that support this micro-architecture.
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generation (int): generation of the micro-architecture, if
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relevant.
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generation (int): generation of the micro-architecture, if relevant.
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cpu_part (str): cpu part of the architecture, if relevant.
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"""
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# pylint: disable=too-many-arguments
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# pylint: disable=too-many-arguments,too-many-instance-attributes
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#: Aliases for micro-architecture's features
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feature_aliases = FEATURE_ALIASES
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def __init__(self, name, parents, vendor, features, compilers, generation=0):
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def __init__(self, name, parents, vendor, features, compilers, generation=0, cpu_part=""):
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self.name = name
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self.parents = parents
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self.vendor = vendor
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self.features = features
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self.compilers = compilers
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# Only relevant for PowerPC
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self.generation = generation
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# Only relevant for AArch64
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self.cpu_part = cpu_part
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# Cache the ancestor computation
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self._ancestors = None
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@ -111,6 +112,7 @@ def __eq__(self, other):
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and self.parents == other.parents # avoid ancestors here
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and self.compilers == other.compilers
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and self.generation == other.generation
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and self.cpu_part == other.cpu_part
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)
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@coerce_target_names
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@ -143,7 +145,8 @@ def __repr__(self):
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cls_name = self.__class__.__name__
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fmt = (
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cls_name + "({0.name!r}, {0.parents!r}, {0.vendor!r}, "
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"{0.features!r}, {0.compilers!r}, {0.generation!r})"
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"{0.features!r}, {0.compilers!r}, generation={0.generation!r}, "
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"cpu_part={0.cpu_part!r})"
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)
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return fmt.format(self)
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@ -190,6 +193,7 @@ def to_dict(self):
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"generation": self.generation,
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"parents": [str(x) for x in self.parents],
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"compilers": self.compilers,
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"cpupart": self.cpu_part,
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}
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@staticmethod
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@ -202,6 +206,7 @@ def from_dict(data) -> "Microarchitecture":
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features=set(data["features"]),
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compilers=data.get("compilers", {}),
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generation=data.get("generation", 0),
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cpu_part=data.get("cpupart", ""),
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)
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def optimization_flags(self, compiler, version):
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@ -360,8 +365,11 @@ def fill_target_from_dict(name, data, targets):
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features = set(values["features"])
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compilers = values.get("compilers", {})
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generation = values.get("generation", 0)
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cpu_part = values.get("cpupart", "")
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targets[name] = Microarchitecture(name, parents, vendor, features, compilers, generation)
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targets[name] = Microarchitecture(
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name, parents, vendor, features, compilers, generation=generation, cpu_part=cpu_part
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)
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known_targets = {}
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data = archspec.cpu.schema.TARGETS_JSON["microarchitectures"]
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@ -2225,10 +2225,14 @@
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],
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"nvhpc": [
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{
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"versions": "21.11:",
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"versions": "21.11:23.8",
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"name": "zen3",
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"flags": "-tp {name}",
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"warnings": "zen4 is not fully supported by nvhpc yet, falling back to zen3"
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"warnings": "zen4 is not fully supported by nvhpc versions < 23.9, falling back to zen3"
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},
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{
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"versions": "23.9:",
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"flags": "-tp {name}"
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}
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]
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}
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@ -2711,7 +2715,8 @@
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"flags": "-mcpu=thunderx2t99"
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}
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]
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}
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},
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"cpupart": "0x0af"
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},
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"a64fx": {
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"from": ["armv8.2a"],
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@ -2779,7 +2784,8 @@
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"flags": "-march=armv8.2-a+crc+crypto+fp16+sve"
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}
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]
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}
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},
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"cpupart": "0x001"
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},
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"cortex_a72": {
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"from": ["aarch64"],
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@ -2816,7 +2822,8 @@
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"flags" : "-mcpu=cortex-a72"
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}
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]
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}
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},
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"cpupart": "0xd08"
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},
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"neoverse_n1": {
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"from": ["cortex_a72", "armv8.2a"],
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@ -2902,7 +2909,8 @@
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"flags": "-tp {name}"
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}
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]
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}
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},
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"cpupart": "0xd0c"
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},
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"neoverse_v1": {
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"from": ["neoverse_n1", "armv8.4a"],
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@ -2926,8 +2934,6 @@
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"lrcpc",
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"dcpop",
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"sha3",
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"sm3",
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"sm4",
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"asimddp",
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"sha512",
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"sve",
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@ -3028,7 +3034,8 @@
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"flags": "-tp {name}"
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}
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]
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}
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},
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"cpupart": "0xd40"
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},
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"neoverse_v2": {
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"from": ["neoverse_n1", "armv9.0a"],
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@ -3052,13 +3059,10 @@
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"lrcpc",
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"dcpop",
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"sha3",
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"sm3",
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"sm4",
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"asimddp",
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"sha512",
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"sve",
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"asimdfhm",
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"dit",
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"uscat",
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"ilrcpc",
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"flagm",
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@ -3066,18 +3070,12 @@
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"sb",
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"dcpodp",
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"sve2",
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"sveaes",
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"svepmull",
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"svebitperm",
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"svesha3",
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"svesm4",
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"flagm2",
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"frint",
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"svei8mm",
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"svebf16",
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"i8mm",
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"bf16",
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"dgh"
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"bf16"
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],
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"compilers" : {
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"gcc": [
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@ -3102,15 +3100,19 @@
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"flags" : "-march=armv8.5-a+sve -mtune=cortex-a76"
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},
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{
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"versions": "10.0:11.99",
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"versions": "10.0:11.3.99",
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"flags" : "-march=armv8.5-a+sve+sve2+i8mm+bf16 -mtune=cortex-a77"
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},
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{
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"versions": "11.4:11.99",
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"flags" : "-mcpu=neoverse-v2"
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},
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{
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"versions": "12.0:12.99",
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"versions": "12.0:12.2.99",
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"flags" : "-march=armv9-a+i8mm+bf16 -mtune=cortex-a710"
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},
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{
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"versions": "13.0:",
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"versions": "12.3:",
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"flags" : "-mcpu=neoverse-v2"
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}
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],
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@ -3145,7 +3147,113 @@
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"flags": "-tp {name}"
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}
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]
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}
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},
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"cpupart": "0xd4f"
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},
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"neoverse_n2": {
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"from": ["neoverse_n1", "armv9.0a"],
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"vendor": "ARM",
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"features": [
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"fp",
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"asimd",
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"evtstrm",
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"aes",
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"pmull",
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"sha1",
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"sha2",
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"crc32",
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"atomics",
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"fphp",
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"asimdhp",
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"cpuid",
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"asimdrdm",
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"jscvt",
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"fcma",
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"lrcpc",
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"dcpop",
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"sha3",
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"asimddp",
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"sha512",
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"sve",
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"asimdfhm",
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"uscat",
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"ilrcpc",
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"flagm",
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"ssbs",
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"sb",
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"dcpodp",
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"sve2",
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"flagm2",
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"frint",
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"svei8mm",
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"svebf16",
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"i8mm",
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"bf16"
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],
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"compilers" : {
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"gcc": [
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{
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"versions": "4.8:5.99",
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"flags": "-march=armv8-a"
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},
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{
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"versions": "6:6.99",
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"flags" : "-march=armv8.1-a"
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},
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{
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"versions": "7.0:7.99",
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"flags" : "-march=armv8.2-a -mtune=cortex-a72"
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},
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{
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"versions": "8.0:8.99",
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"flags" : "-march=armv8.4-a+sve -mtune=cortex-a72"
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},
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{
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"versions": "9.0:9.99",
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"flags" : "-march=armv8.5-a+sve -mtune=cortex-a76"
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},
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{
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"versions": "10.0:10.99",
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"flags" : "-march=armv8.5-a+sve+sve2+i8mm+bf16 -mtune=cortex-a77"
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},
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{
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"versions": "11.0:",
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"flags" : "-mcpu=neoverse-n2"
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}
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],
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"clang" : [
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{
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"versions": "9.0:10.99",
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"flags" : "-march=armv8.5-a+sve"
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},
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{
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"versions": "11.0:13.99",
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"flags" : "-march=armv8.5-a+sve+sve2+i8mm+bf16"
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},
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{
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"versions": "14.0:15.99",
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"flags" : "-march=armv9-a+i8mm+bf16"
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},
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{
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"versions": "16.0:",
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"flags" : "-mcpu=neoverse-n2"
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}
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],
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"arm" : [
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{
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"versions": "23.04.0:",
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"flags" : "-mcpu=neoverse-n2"
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}
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],
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"nvhpc" : [
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{
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"versions": "23.3:",
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"name": "neoverse-n1",
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"flags": "-tp {name}"
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}
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]
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},
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"cpupart": "0xd49"
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},
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"m1": {
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"from": ["armv8.4a"],
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@ -3211,7 +3319,8 @@
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"flags" : "-mcpu=apple-m1"
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}
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]
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}
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},
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"cpupart": "0x022"
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},
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"m2": {
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"from": ["m1", "armv8.5a"],
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@ -3289,7 +3398,8 @@
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"flags" : "-mcpu=apple-m2"
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}
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]
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}
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},
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"cpupart": "0x032"
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},
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"arm": {
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"from": [],
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@ -52,6 +52,9 @@
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}
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}
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}
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},
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"cpupart": {
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"type": "string"
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}
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},
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"required": [
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@ -107,4 +110,4 @@
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"additionalProperties": false
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}
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}
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}
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}
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